1. Field of the Invention
This invention relates to phase-locked loop controls for reading data from storage media and, in particular, to phase-locked loop controls for reading data off of high density media such as the IBM 3480 cartridge storage system.
2. Discussion of Prior Art
It is conventional in high performance disk, tape or optical products to employ a phase-locked loop (PLL) in the read channels. Phase-locked loop control functions to track speed variations of the incoming data read from the media.
An example of a conventional tape product that incorporates a phase-locked loop (PLL) control is shown in FIG. 1. In FIG. 1, a storage media 10 such as the IBM 3480 cartridge is read by a tape head 20 which delivers output signals through an automatic gain control circuit 30. The signals from the automatic gain control circuit 30 enter a filter and equalizer circuit 40 which filters the signal and provides equalization thereto. The signals are then delivered to a peak detector 50 which for every peak delivers a digital value representing a "one" that was previously written on the media. The peak detector then delivers the signal to a conventional phase-locked loop circuit 60 which, as mentioned, tracks speed variations in the incoming data on storage media 10. The data from the phase-locked loop 60 is delivered to a conventional data separator and error correction circuit for delivery as digital bytes of data information 90 into the system.
In FIG. 2, the phase-locked loop circuit 60 is shown to include a data selector which obtains the incoming data from the peak detector 50. The data selector circuit 200 is conventional. The output of the data selector is delivered into the phase detector 210. Phase detector 210 compares the incoming signal on line 202 to an internal clock and if there is any difference between the phase of the clock and the phase of the data on line 202, a charge pump 220 is selectively activated. For example, if the data pulse precedes the clock pulse, this is an early phase error and lead 212 becomes activated to cause the charge pump circuit 220 to deliver more current into the filter 225 which is converted to a voltage. This causes the voltage controlled oscillator 230 to increase frequency in order to obtain a phase match. Likewise, if the data on lead 202 follows the clock pulse, a late signal is delivered over lead 214 to the charge pump 220 to cause the frequency of the voltage control oscillator 230 to slow down. In a predetermined number of clock cycles, the phase-locked loop circuit 60 is in synchronism with the data. An example of a prior art phase-locked loop approach is found in U.S. Pat. No. 4,068,198.
Variations in the frequency of the signal on lead 202 can be due to a number of things including defects in the media which could cause dropouts or missing pulses, speed variations, and head flying irregularities. The oscillator 230 is typically a 1.95 MHz clock for the 3480 environment.
In FIG. 3, the prior art data format for the IBM 3480 high density tape storage sub-system is set forth showing a preamble field 300 comprising nine to thirteen frames of all "ones." Following the preamble field is a synchronization (SYNC) field 310 which normally is two frames which precedes a variable length data field DB1 and DB2. Other special purpose frames are not shown.
The phase-locked loop 60 operates in a high gain mode (HGM) during the preamble frames 300. During this mode of operation, the phase detector 210 matches the phase for each "one" read in the preamble. In the high gain mode, the phase-locked loop control 60 synchronizes the oscillator 230 with the frequency of the incoming data within two to five frames. After seven frames of the preamble frames 300, the phase-locked loop 60 enters the low gain mode (LGM) which provides phase comparisons only on the edges of data "ones".
Proper synchronization based upon acquisitions of the preamble are not always successful. For example, defects in the magnetic media can obscure the data. Tape drives may also exhibit varying degrees of skew across the head so that the preamble is not aligning with all tracks simultaneously. Furthermore, the tape could also flutter across the head and thereby obscure the data. During the inter block gap (IBG), the phase-locked loop control 60 is idle.
Problem -- The problem with prior phase-locked loop controls 60 occurs if errors occur in the preamble field 300. If any of the "ones" are actually zeros, an error occurs, and as mentioned, this may be due to a number of factors. The presence of errors in the preamble field causes problems with the phase detector 210 in properly matching the phase of the voltage controlled oscillator 230 with the incoming data. For example, a missing pulse would cause a substantial late error signal on lead 214 causing the VCO 230 to slow down. Several missing pulses in a row would clearly put the VCO 230 out of lock with the incoming data.
If there is corruption in the preamble, the phase-locked loop comparisons will continue with the voltage controlled oscillator becoming out of lock. For example, if data pulses are missing in the preamble, the voltage controlled oscillator will incorrectly slow to what it determines to be a much slower frequency of the preamble data. Even if the corruption goes away in the preamble and correct data returns, the phase-locked loop control may not have enough time to acquire the proper frequency of the incoming data thus lowering the probability of accurate acquisition.
Solution -- The present invention provides a solution to this problem to better insure the integrity of operation of the phase-locked loop control 60.
The present invention adds a new circuit, a pattern qualifier, to overcome the above problem and to achieve a better probability of acquisition. The present invention is designed to check the preamble data for proper bit spacing and if missing or extra pulses are present, the pattern qualifier disables a phase comparison from taking place. Thus the voltage controlled oscillator frequency remains constant during the periods of corruption until the proper bit spacing returns to the preamble. Hence, during the periods of corrupt data, the phase-locked loop control as modified by the teachings of the present invention will not attempt to find a new and incorrect frequency as would occur under the prior art approaches.